Leveraging speculative architectures for runtime program validation
Program execution can be tampered with by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been prese...
- Autores:
- Tipo de recurso:
- Fecha de publicación:
- 2013
- Institución:
- Universidad Tecnológica de Bolívar
- Repositorio:
- Repositorio Institucional UTB
- Idioma:
- eng
- OAI Identifier:
- oai:repositorio.utb.edu.co:20.500.12585/9074
- Acceso en línea:
- https://hdl.handle.net/20.500.12585/9074
- Palabra clave:
- Control flow validation
Program validation
Security attacks
Branch target buffers
Computer system security
Control flows
Hardware-based approach
Performance penalties
Program validation
Security attacks
Software vulnerabilities
Digital storage
Hardware
- Rights
- restrictedAccess
- License
- http://creativecommons.org/licenses/by-nc-nd/4.0/
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Leveraging speculative architectures for runtime program validation |
| title |
Leveraging speculative architectures for runtime program validation |
| spellingShingle |
Leveraging speculative architectures for runtime program validation Control flow validation Program validation Security attacks Branch target buffers Computer system security Control flows Hardware-based approach Performance penalties Program validation Security attacks Software vulnerabilities Digital storage Hardware |
| title_short |
Leveraging speculative architectures for runtime program validation |
| title_full |
Leveraging speculative architectures for runtime program validation |
| title_fullStr |
Leveraging speculative architectures for runtime program validation |
| title_full_unstemmed |
Leveraging speculative architectures for runtime program validation |
| title_sort |
Leveraging speculative architectures for runtime program validation |
| dc.subject.keywords.none.fl_str_mv |
Control flow validation Program validation Security attacks Branch target buffers Computer system security Control flows Hardware-based approach Performance penalties Program validation Security attacks Software vulnerabilities Digital storage Hardware |
| topic |
Control flow validation Program validation Security attacks Branch target buffers Computer system security Control flows Hardware-based approach Performance penalties Program validation Security attacks Software vulnerabilities Digital storage Hardware |
| description |
Program execution can be tampered with by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. We propose a new hardware-based approach by leveraging the existing speculative architectures for runtime program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at runtime. Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead. © 2013 ACM. |
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2013 |
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2013 |
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2020-03-26T16:32:53Z |
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2020-03-26T16:32:53Z |
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http://purl.org/coar/version/c_970fb48d4fbd8a85 |
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Artículo |
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Transactions on Embedded Computing Systems; Vol. 13, Núm. 1 |
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15399087 |
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https://hdl.handle.net/20.500.12585/9074 |
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10.1145/2512456 |
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Universidad Tecnológica de Bolívar |
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Repositorio UTB |
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26325154200 7103059457 |
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Transactions on Embedded Computing Systems; Vol. 13, Núm. 1 15399087 10.1145/2512456 Universidad Tecnológica de Bolívar Repositorio UTB 26325154200 7103059457 |
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https://hdl.handle.net/20.500.12585/9074 |
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eng |
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eng |
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Atribución-NoComercial 4.0 Internacional |
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2020-03-26T16:32:53Z2020-03-26T16:32:53Z2013Transactions on Embedded Computing Systems; Vol. 13, Núm. 115399087https://hdl.handle.net/20.500.12585/907410.1145/2512456Universidad Tecnológica de BolívarRepositorio UTB263251542007103059457Program execution can be tampered with by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. We propose a new hardware-based approach by leveraging the existing speculative architectures for runtime program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at runtime. Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead. © 2013 ACM.Recurso electrónicoapplication/pdfenghttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/restrictedAccessAtribución-NoComercial 4.0 Internacionalhttp://purl.org/coar/access_right/c_16echttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84883857670&doi=10.1145%2f2512456&partnerID=40&md5=64152a241d75d7cc5bec7937d4c39862Leveraging speculative architectures for runtime program validationinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionArtículohttp://purl.org/coar/version/c_970fb48d4fbd8a85http://purl.org/coar/resource_type/c_2df8fbb1Control flow validationProgram validationSecurity attacksBranch target buffersComputer system securityControl flowsHardware-based approachPerformance penaltiesProgram validationSecurity attacksSoftware vulnerabilitiesDigital storageHardwareSantos J.C.M.Fei Y.Arora, D., Ravi, S., Raghunathan, A., Jha, N.K., Secure embedded processing through hardwareassisted run-time monitoring (2005) Proceedings of the Conference on Design, Automation & Test, pp. 178-183Austin, T., Larson, E., Ernst, D., SimpleScalar: An infrastructure for computer system modeling (2002) Comput, 35 (2), pp. 59-67Borin, E., Wang, C., Wu, Y., Araujo, G., Dynamic binary control-flow errors detection (2005) ACM SIGARCH Comput. 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