Leveraging speculative architectures for runtime program validation

Program execution can be tampered with by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. We propose a new hardware-based approach by leveraging the existing speculative architectures for runtime program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at runtime. Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead. © 2013 ACM.

• Fecha de publicación: 2013
• Institución: Universidad Tecnológica de Bolívar
• Repositorio: Repositorio Institucional UTB
• Idioma: eng
• OAI Identifier: oai:repositorio.utb.edu.co:20.500.12585/9074
• Acceso en línea: https://hdl.handle.net/20.500.12585/9074
• Palabra clave: Control flow validation; Program validation; Security attacks; Branch target buffers; Computer system security; Control flows; Hardware-based approach; Performance penalties; Program validation; Security attacks; Software vulnerabilities; Digital storage; Hardware
• Rights: restrictedAccess
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/