On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation
In built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax+20, where Smax is the maximum number of specified bits in any test cube of t...
- Autores:
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- Fecha de publicación:
- 2016
- Institución:
- Universidad Tecnológica de Bolívar
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- Repositorio Institucional UTB
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- eng
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- Acceso en línea:
- https://hdl.handle.net/20.500.12585/8992
- Palabra clave:
- Algorithm design and analysis
Linear systems
Mathematical model
Polynomials
Test pattern generators
Upper bound
Computation theory
Data compression
Geometry
Linear systems
Mathematical models
Algorithm design and analysis
Berlekamp-Massey algorithm
Characteristic polynomials
Deterministic test pattern
Polynomial degree
Test pattern generator
Test-set compression
Upper bound
Polynomials
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dc.title.none.fl_str_mv |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation |
title |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation |
spellingShingle |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation Algorithm design and analysis Linear systems Mathematical model Polynomials Test pattern generators Upper bound Computation theory Data compression Geometry Linear systems Mathematical models Algorithm design and analysis Berlekamp-Massey algorithm Characteristic polynomials Deterministic test pattern Polynomial degree Test pattern generator Test-set compression Upper bound Polynomials |
title_short |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation |
title_full |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation |
title_fullStr |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation |
title_full_unstemmed |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation |
title_sort |
On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation |
dc.subject.keywords.none.fl_str_mv |
Algorithm design and analysis Linear systems Mathematical model Polynomials Test pattern generators Upper bound Computation theory Data compression Geometry Linear systems Mathematical models Algorithm design and analysis Berlekamp-Massey algorithm Characteristic polynomials Deterministic test pattern Polynomial degree Test pattern generator Test-set compression Upper bound Polynomials |
topic |
Algorithm design and analysis Linear systems Mathematical model Polynomials Test pattern generators Upper bound Computation theory Data compression Geometry Linear systems Mathematical models Algorithm design and analysis Berlekamp-Massey algorithm Characteristic polynomials Deterministic test pattern Polynomial degree Test pattern generator Test-set compression Upper bound Polynomials |
description |
In built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax+20, where Smax is the maximum number of specified bits in any test cube of the test set. By fixing the polynomial a priori a linear system only needs to be solved to compute the required LFSR initial states (seeds) to generate the target test cubes, but the disadvantage is that the polynomial degree (length of the LFSR and seed bit size) may be too large and the fault coverage cannot be guaranteed. In this paper we address the problem of computing a polynomial of small degree directly from the given test set without having to solve multiple non-linear systems and fixing a priori the polynomial degree. The proposed method uses an adaptation of the Berlekamp-Massey algorithm and the Sidorenko-Bossert theorem to perform the computation. In addition, the method guarantees (by design) that all the test cubes in the given test set are generated, thereby achieving 100% coverage, which cannot be guaranteed under the 'trial-and-error' Smax+20 rule. Experimental results verify the advantages that the proposed methodology offers in terms of reduced polynomial degree and 100% coverage. © 1968-2012 IEEE. |
publishDate |
2016 |
dc.date.issued.none.fl_str_mv |
2016 |
dc.date.accessioned.none.fl_str_mv |
2020-03-26T16:32:44Z |
dc.date.available.none.fl_str_mv |
2020-03-26T16:32:44Z |
dc.type.coarversion.fl_str_mv |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
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http://purl.org/coar/resource_type/c_2df8fbb1 |
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info:eu-repo/semantics/article |
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info:eu-repo/semantics/publishedVersion |
dc.type.spa.none.fl_str_mv |
Artículo |
status_str |
publishedVersion |
dc.identifier.citation.none.fl_str_mv |
IEEE Transactions on Computers; Vol. 65, Núm. 2; pp. 664-669 |
dc.identifier.issn.none.fl_str_mv |
00189340 |
dc.identifier.uri.none.fl_str_mv |
https://hdl.handle.net/20.500.12585/8992 |
dc.identifier.doi.none.fl_str_mv |
10.1109/TC.2015.2428697 |
dc.identifier.instname.none.fl_str_mv |
Universidad Tecnológica de Bolívar |
dc.identifier.reponame.none.fl_str_mv |
Repositorio UTB |
dc.identifier.orcid.none.fl_str_mv |
57197327858 7004389110 |
identifier_str_mv |
IEEE Transactions on Computers; Vol. 65, Núm. 2; pp. 664-669 00189340 10.1109/TC.2015.2428697 Universidad Tecnológica de Bolívar Repositorio UTB 57197327858 7004389110 |
url |
https://hdl.handle.net/20.500.12585/8992 |
dc.language.iso.none.fl_str_mv |
eng |
language |
eng |
dc.rights.coar.fl_str_mv |
http://purl.org/coar/access_right/c_16ec |
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http://creativecommons.org/licenses/by-nc-nd/4.0/ |
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Atribución-NoComercial 4.0 Internacional |
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http://creativecommons.org/licenses/by-nc-nd/4.0/ Atribución-NoComercial 4.0 Internacional http://purl.org/coar/access_right/c_16ec |
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Recurso electrónico |
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application/pdf |
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IEEE Computer Society |
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IEEE Computer Society |
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2020-03-26T16:32:44Z2020-03-26T16:32:44Z2016IEEE Transactions on Computers; Vol. 65, Núm. 2; pp. 664-66900189340https://hdl.handle.net/20.500.12585/899210.1109/TC.2015.2428697Universidad Tecnológica de BolívarRepositorio UTB571973278587004389110In built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax+20, where Smax is the maximum number of specified bits in any test cube of the test set. By fixing the polynomial a priori a linear system only needs to be solved to compute the required LFSR initial states (seeds) to generate the target test cubes, but the disadvantage is that the polynomial degree (length of the LFSR and seed bit size) may be too large and the fault coverage cannot be guaranteed. In this paper we address the problem of computing a polynomial of small degree directly from the given test set without having to solve multiple non-linear systems and fixing a priori the polynomial degree. The proposed method uses an adaptation of the Berlekamp-Massey algorithm and the Sidorenko-Bossert theorem to perform the computation. In addition, the method guarantees (by design) that all the test cubes in the given test set are generated, thereby achieving 100% coverage, which cannot be guaranteed under the 'trial-and-error' Smax+20 rule. Experimental results verify the advantages that the proposed methodology offers in terms of reduced polynomial degree and 100% coverage. © 1968-2012 IEEE.Recurso electrónicoapplication/pdfengIEEE Computer Societyhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/restrictedAccessAtribución-NoComercial 4.0 Internacionalhttp://purl.org/coar/access_right/c_16echttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84962090065&doi=10.1109%2fTC.2015.2428697&partnerID=40&md5=d8909b99a8d0de0e0b965b6fd72ea7f0On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generationinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionArtículohttp://purl.org/coar/version/c_970fb48d4fbd8a85http://purl.org/coar/resource_type/c_2df8fbb1Algorithm design and analysisLinear systemsMathematical modelPolynomialsTest pattern generatorsUpper boundComputation theoryData compressionGeometryLinear systemsMathematical modelsAlgorithm design and analysisBerlekamp-Massey algorithmCharacteristic polynomialsDeterministic test patternPolynomial degreeTest pattern generatorTest-set compressionUpper boundPolynomialsAcevedo Patiño, ÓscarKagaris D.Acevedo, O., Kagaris, D., Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG (2012) Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst, pp. 233-238Bakshi, D., Hsiao, M.S., LFSR seed computation, and reduction using SMT-based fault-chaining (2013) Proc. Des., Autom. Test Eur. Conf. Exhib, pp. 1071-1076Bardell, P.H., McAnney, W.H., Savir, J., (1987) Built-In Test for VLSI: Pseudorandom Techniques, , New York NY USA WileyFarebrother, R.W., (1988) Linear Least Squares Computations, , New York NY USA Marcel DekkerGustavson, F.G., Analysis of the Berlekamp-Massey linear feedback shiftregister synthesis algorithm (1976) IBM J. Res. Develop, 20 (3), pp. 204-212. , MayHellebrand, S., Tarnick, S., Rajski, J., Courtois, B., Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift register (1992) Proc. Int. Test Conf, pp. 120-129Huang, L.-R., Jou, J.-Y., Kuo, S.-Y., Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR (1997) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 16 (9), pp. 1015-1024. , SepKalligeros, E., Kavousianos, X., Nikolos, D., Multiphase BIST A new reseeding technique for high test-data compression (2004) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 23 (10), pp. 1429-1446. , OctKavousianos, X., Tenentes, V., Chakrabarty, K., Kalligeros, E., Defectoriented LFSR reseeding to target unmodeled defects using stuck-at test sets (2011) IEEE Trans. Very Large Scale Integration Syst, 19 (12), pp. 2330-2335. , DecKim, H.-S., Kang, S., Increasing encoding efficiency of LFSR reseedingbased test compression (2006) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 25 (5), pp. 913-917. , MayKoenemann, B., LFSR-coded test patterns for scan designs (1991) Proc. Eur. Test Conf, pp. 237-242Kongtim, P., Reungpeerakul, T., Parallel LFSR reseeding with selection register for mixed-mode BIST (2010) Proc. IEEE Asian Test Symp, pp. 153-158Koutsoupia, M., Kalligeros, E., Kavousianos, X., Nikolos, D., LFSRbased test-data compression with self-stoppable seeds (2009) Proc. Des., Autom. Test Eur. Conf. Exhib, pp. 1482-1487Krishna, C.V., Jas, A., Touba, N.A., Test vector encoding using partial LFSR reseeding (2001) Proc. Int. Test Conf, pp. 885-893Krishna, C.V., Touba, N.A., Reducing test data volume using LFSR reseeding with seed compression (2002) Proc. Int. Test Conf, pp. 321-330Lee, J., Touba, N.A., LFSR-reseeding scheme achieving low-power dissipation during test (2007) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 26 (2), pp. 396-401. , FebLee, L.-J., Tseng, W.-D., Yang, W.-T., Dual-LFSR reseeding for low power testing (2012) Proc. Int. Workshop Microprocessor Test Verification, pp. 30-34Lien, W.-C., Lee, K.-J., Hsieh, T.-Y., Chakrabarty, K., A new LFSR reseeding scheme via internal response feedback (2013) Proc. IEEE Asian Test Symp, pp. 97-102Lien, W.-C., Lee, K.-J., Hsieh, T.-Y., A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length, and test data volume (2012) Proc. IEEE Asian Test Symp, pp. 278-283Massey, J., Shift-register synthesis, and BCH decoding (1969) IEEE Trans. Inf. Theory, 15 (1), pp. 122-127Rajski, J., Tyszer, J., Primitive polynomials over GF(2) of degree up to 660 with uniformly distributed coefficients (2003) J. Electron. Testing, 19 (6), pp. 645-657Sidorenko, V.R., Bossert, M., Synthesizing all linearized shift-registers of the minimal or required length (2010) Proc. Int. ITG Conf. Source, and Channel Coding, pp. 1-6Souza, C.P., Assis, F.M., Freire, R.C.S., Mixed test pattern generation using a single parallel LFSR (2006) Proc. IEEE Instrumentation Measurement Technol. Conf, pp. 1114-1118Yilmaz, M., Chakrabarty, K., Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects (2009) Proc. Des., Autom. Test Eur. Conf. Exhib, pp. 1488-1493Wang, L.-T., Chang, Y.-W., Cheng, K.-T., (2009) Electronic Design Automation Syn Thesis, Verification, and Test, , Burlington, MA, USA: Morgan-KaufmannWang, Z., Fang, H., Chakrabarty, K., Bienek, M., Deviation-based LFSR reseeding for test-data compression (2009) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 28 (2), pp. 259-271. , Febhttp://purl.org/coar/resource_type/c_6501THUMBNAILMiniProdInv.pngMiniProdInv.pngimage/png23941https://repositorio.utb.edu.co/bitstream/20.500.12585/8992/1/MiniProdInv.png0cb0f101a8d16897fb46fc914d3d7043MD5120.500.12585/8992oai:repositorio.utb.edu.co:20.500.12585/89922023-04-21 15:21:58.256Repositorio Institucional UTBrepositorioutb@utb.edu.co |