An area efficient high speed, fully on-chip low dropout –LDO- voltage regulator
(Eng) This paper presents the design of a low-dropout voltage regulator which has a low area and power consumption, as well as an improved transient response. The area reduction is achieved by biasing the power transistor in the triode region. In addition, a dynamic bias network is used in order to...
- Autores:
-
Amaya, Andrés F.
Gómez, Héctor I.
Espinosa, Guillermo
- Tipo de recurso:
- Article of journal
- Fecha de publicación:
- 2015
- Institución:
- Universidad del Valle
- Repositorio:
- Repositorio Digital Univalle
- Idioma:
- eng
- OAI Identifier:
- oai:bibliotecadigital.univalle.edu.co:10893/18501
- Acceso en línea:
- https://hdl.handle.net/10893/18501
- Palabra clave:
- Polarización adaptativa
Polarización dinámica
Regulador lineal
Sin condensador de salida
Respuesta transitoria
Adaptive bias
Dynamic bias
Linear regulator
Output capacitor less
Transient response
- Rights
- closedAccess
- License
- http://purl.org/coar/access_right/c_14cb