Intellectual property core for serial communication protocols in FPGA
Throughout this project, a methodology based on Intellectual Property (IP) Cores is implemented for two serial communication protocols, one asynchronous (UART) and one synchronous (SPI), on an FPGA board. With this in mind, a high-level software model is proposed as a reference to a low-level RTL al...
- Autores:
-
Acosta David, Favio Andrés
- Tipo de recurso:
- Trabajo de grado de pregrado
- Fecha de publicación:
- 2020
- Institución:
- Universidad de los Andes
- Repositorio:
- Séneca: repositorio Uniandes
- Idioma:
- eng
- OAI Identifier:
- oai:repositorio.uniandes.edu.co:1992/51530
- Acceso en línea:
- http://hdl.handle.net/1992/51530
- Palabra clave:
- Microcontroladores
Matrices lógicas programables por el usuario
Sistemas de transmisión de datos
Ingeniería
- Rights
- openAccess
- License
- https://repositorio.uniandes.edu.co/static/pdf/aceptacion_uso_es.pdf
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Al consultar y hacer uso de este recurso, está aceptando las condiciones de uso establecidas por los autores.https://repositorio.uniandes.edu.co/static/pdf/aceptacion_uso_es.pdfinfo:eu-repo/semantics/openAccesshttp://purl.org/coar/access_right/c_abf2Segura Quijano, Fredy Enriquevirtual::13629-1Acosta David, Favio Andrés8d8a13ba-91e2-4fbc-b6ae-370a7b6c95a1500Higuera Arias, Carolina2021-08-10T18:29:24Z2021-08-10T18:29:24Z2020http://hdl.handle.net/1992/5153022665.pdfinstname:Universidad de los Andesreponame:Repositorio Institucional Sénecarepourl:https://repositorio.uniandes.edu.co/Throughout this project, a methodology based on Intellectual Property (IP) Cores is implemented for two serial communication protocols, one asynchronous (UART) and one synchronous (SPI), on an FPGA board. With this in mind, a high-level software model is proposed as a reference to a low-level RTL algorithm that validates its behavior. In addition, a physical implementation is built to corroborate the correct functionality of the developed protocols.A lo largo de este proyecto se implementa una metodología basada en Módulos de Propiedad Intelectual para dos protocolos de comunicación serial asíncrona (UART) y síncrona (SPI), en una tarjeta FPGA. Con esto en mente, se propone un modelo en alto nivel equivalente al algoritmo RTL de bajo nivel que valide su comportamiento. Asimismo, se construye una implementación física que corrobore la correcta funcionalidad de los protocolos desarrollados.Ingeniero ElectrónicoPregrado124 hojasapplication/pdfengUniversidad de los AndesIngeniería ElectrónicaFacultad de IngenieríaDepartamento de Ingeniería Eléctrica y ElectrónicaIntellectual property core for serial communication protocols in FPGATrabajo de grado - Pregradoinfo:eu-repo/semantics/bachelorThesishttp://purl.org/coar/resource_type/c_7a1fhttp://purl.org/coar/version/c_970fb48d4fbd8a85Texthttp://purl.org/redcol/resource_type/TPMicrocontroladoresMatrices lógicas programables por el usuarioSistemas de transmisión de datosIngeniería201612431Publicationhttps://scholar.google.es/citations?user=xw2k1CIAAAAJvirtual::13629-10000-0001-7757-1432virtual::13629-1https://scienti.minciencias.gov.co/cvlac/visualizador/generarCurriculoCv.do?cod_rh=0000051497virtual::13629-17684cb09-6991-4ac4-aff9-b29fe065439fvirtual::13629-17684cb09-6991-4ac4-aff9-b29fe065439fvirtual::13629-1ORIGINAL22665.pdfapplication/pdf4655464https://repositorio.uniandes.edu.co/bitstreams/3e62f049-3b9a-49ff-895b-b2789e91a689/downloadb7066ad947daffa0d2c4ddfd6f1cd263MD51TEXT22665.pdf.txt22665.pdf.txtExtracted texttext/plain314497https://repositorio.uniandes.edu.co/bitstreams/c127bffc-5571-4dfc-b6b9-294943da9d16/download05bd9803af50ca51bf7f744ea9f6e00cMD54THUMBNAIL22665.pdf.jpg22665.pdf.jpgIM Thumbnailimage/jpeg10000https://repositorio.uniandes.edu.co/bitstreams/19d3f89c-e23b-47e3-8eb2-71d7233e7fe9/download5ec3da5339b2b2429eb36f3a6b398518MD551992/51530oai:repositorio.uniandes.edu.co:1992/515302024-03-13 14:59:09.773https://repositorio.uniandes.edu.co/static/pdf/aceptacion_uso_es.pdfopen.accesshttps://repositorio.uniandes.edu.coRepositorio institucional Sénecaadminrepositorio@uniandes.edu.co |
| dc.title.spa.fl_str_mv |
Intellectual property core for serial communication protocols in FPGA |
| title |
Intellectual property core for serial communication protocols in FPGA |
| spellingShingle |
Intellectual property core for serial communication protocols in FPGA Microcontroladores Matrices lógicas programables por el usuario Sistemas de transmisión de datos Ingeniería |
| title_short |
Intellectual property core for serial communication protocols in FPGA |
| title_full |
Intellectual property core for serial communication protocols in FPGA |
| title_fullStr |
Intellectual property core for serial communication protocols in FPGA |
| title_full_unstemmed |
Intellectual property core for serial communication protocols in FPGA |
| title_sort |
Intellectual property core for serial communication protocols in FPGA |
| dc.creator.fl_str_mv |
Acosta David, Favio Andrés |
| dc.contributor.advisor.none.fl_str_mv |
Segura Quijano, Fredy Enrique |
| dc.contributor.author.none.fl_str_mv |
Acosta David, Favio Andrés |
| dc.contributor.jury.none.fl_str_mv |
Higuera Arias, Carolina |
| dc.subject.armarc.none.fl_str_mv |
Microcontroladores Matrices lógicas programables por el usuario Sistemas de transmisión de datos |
| topic |
Microcontroladores Matrices lógicas programables por el usuario Sistemas de transmisión de datos Ingeniería |
| dc.subject.themes.none.fl_str_mv |
Ingeniería |
| description |
Throughout this project, a methodology based on Intellectual Property (IP) Cores is implemented for two serial communication protocols, one asynchronous (UART) and one synchronous (SPI), on an FPGA board. With this in mind, a high-level software model is proposed as a reference to a low-level RTL algorithm that validates its behavior. In addition, a physical implementation is built to corroborate the correct functionality of the developed protocols. |
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2020 |
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2020 |
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2021-08-10T18:29:24Z |
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2021-08-10T18:29:24Z |
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http://purl.org/coar/version/c_970fb48d4fbd8a85 |
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info:eu-repo/semantics/bachelorThesis |
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http://purl.org/coar/resource_type/c_7a1f |
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http://hdl.handle.net/1992/51530 |
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22665.pdf |
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reponame:Repositorio Institucional Séneca |
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repourl:https://repositorio.uniandes.edu.co/ |
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http://hdl.handle.net/1992/51530 |
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22665.pdf instname:Universidad de los Andes reponame:Repositorio Institucional Séneca repourl:https://repositorio.uniandes.edu.co/ |
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124 hojas |
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Universidad de los Andes |
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Ingeniería Electrónica |
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Facultad de Ingeniería |
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Departamento de Ingeniería Eléctrica y Electrónica |
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Universidad de los Andes |
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