Study of electromigration and ir-drop effects for chip reliability

Una metodología para analizar los efectos generados por la Electromigración (EM) y el IR-drop en tecnología CMOS 130nm TSMC se llevó a cabo en este trabajo. La metodología implementada evita el sobredimensionamiento de la vista layout en los circuitos diseñados y reduce el tiempo de trabajo utilizad...

Full description

Autores:
Lozano Carvajal, Juan Pablo
Tipo de recurso:
http://purl.org/coar/version/c_b1a7d7d4d402bcce
Fecha de publicación:
2016
Institución:
Universidad Industrial de Santander
Repositorio:
Repositorio UIS
Idioma:
spa
OAI Identifier:
oai:noesis.uis.edu.co:20.500.14071/35032
Acceso en línea:
https://noesis.uis.edu.co/handle/20.500.14071/35032
https://noesis.uis.edu.co
Palabra clave:
130Nm
Cmos
Electromigracion
Ir-Drop
Confiabilidad
Microelectronica.
A methodology to analyze Electromigration (EM) and IR-drop effects in TSMC 130nm CMOS technology was implemented in this work. The implemented methodology avoids oversizing of the designed circuit layout and reduces the working time used to fix them. Analog
mixed-signal and digital circuits (amplifiers
comparators
filters
phase mixers
ADCs
bandgap voltage reference
charge pumps) were analyzed showing on the layout the circuit structures where EM and IR-drop effect are critical. Among the most common solutions used in this paper to solve the defects found in the layout view of the circuits analyzed are. The modification of the geometry of the interconnection layers with current density levels higher than allowed by the company that produces the integrated circuits (Foundry); The reduction in the supply voltages to avoid high levels of current densities sacrificing circuit performance and reduction in the operating frequency of electronic circuits that do not allow to modify the geometry of the interconnections layers by lack of free space and / or failure of the layout design rules (DRC). The presented results indicate that the implemented methodology is very efficient detecting bottleneck regions
which guarantees the electrical integrity of the produced chip during long operation time and extensive use.
Rights
License
Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)