DRAM size independence in single-core processors using gem5

Energy consumption, speed of execution, and integrated circuit area have become important topics in recent years thanks to the growth of the market for mobile devices and the manufacturers of these devices who try to push the limits of their products while maintaining an affordable price. In that ra...

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Autores:
Gallego-Garcés, Andrés
Eslava-Garzón, Sebastián
Tipo de recurso:
Fecha de publicación:
2016
Institución:
Universidad Santo Tomás
Repositorio:
Universidad Santo Tomás
Idioma:
spa
OAI Identifier:
oai:repository.usta.edu.co:11634/4924
Acceso en línea:
http://revistas.ustatunja.edu.co/index.php/ingeniomagno/article/view/1091
Palabra clave:
cache
dram
gem5
memory hierarchy-
parsec
caché
DRAM
gem5
jerarquía de memorias
PARSEC
cache
dram
gem5
hierarquia de momórias
parsec
Rights
License
Derechos de autor 2016 Ingenio Magno