Static Worst-Case Execution Time Optimization using DPSO for ASIP Architecture

Introduction: The application of specific instructions significantly improves energy, performance, and code size of configurable processors. The design of these instructions is performed by the conversion of patterns related to application-specific operations into effective complex instructions. Thi...

Full description

Autores:

Venkanna, Mood
Rao, Rameshwar

Tipo de recurso:

Article of journal

Fecha de publicación:

2018

Institución:

Universidad Cooperativa de Colombia

Repositorio:

Repositorio UCC

Idioma:

eng

OAI Identifier:

oai:repository.ucc.edu.co:20.500.12494/9444

Acceso en línea:

https://revistas.ucc.edu.co/index.php/in/article/view/2230
https://hdl.handle.net/20.500.12494/9444

Palabra clave:

Rights

openAccess

License

Copyright (c) 2018 Journal of Engineering and Education