Intellectual property core for serial communication protocols in FPGA (2020)
Throughout this project, a methodology based on Intellectual Property (IP) Cores is implemented for two serial communication protocols, one asynchronous (UART) and one synchronous (SPI), on an FPGA board. With this in mind, a high-level software model is proposed as a reference to a low-level RTL algorithm that validates its behavior. In addition, a physical implementation is built to corroborate the correct functionality of the developed protocols.