Simple generation of threshold for images binarization on FPGA

This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obta...

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Autores:
Ieno, Egidio
Garcés, Luis Manuel
Cabrera, Alejandro José
Pimenta, Tales Cleber
Tipo de recurso:
Article of journal
Fecha de publicación:
2015
Institución:
Universidad Nacional de Colombia
Repositorio:
Universidad Nacional de Colombia
Idioma:
spa
OAI Identifier:
oai:repositorio.unal.edu.co:unal/67650
Acceso en línea:
https://repositorio.unal.edu.co/handle/unal/67650
http://bdigital.unal.edu.co/68679/
Palabra clave:
62 Ingeniería y operaciones afines / Engineering
Digital image processing
threshold
FPGA
System Generator®
MATLAB®/Simulink®.
Procesamiento digital de imágenes
umbral
FPGA
System Generator®
Matlab®/Simulink®.
Rights
openAccess
License
Atribución-NoComercial 4.0 Internacional
Description
Summary:This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu’s method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by model-based design supported by the MATLAB®/Simulink® and Xilinx System Generator® tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in co-simulation system and show the effectiveness of the proposed method.