IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION
The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the accuracy is very high and there are no conditions or restrictions for the operation to be fulfilled. It also consumes much less hardware surface than...
- Autores:
-
López, Jorge H.
Restrepo, Johans
Tobón, Jorge E.
- Tipo de recurso:
- Article of journal
- Fecha de publicación:
- 2018
- Institución:
- Universidad Nacional de Colombia
- Repositorio:
- Universidad Nacional de Colombia
- Idioma:
- spa
- OAI Identifier:
- oai:repositorio.unal.edu.co:unal/67295
- Acceso en línea:
- https://repositorio.unal.edu.co/handle/unal/67295
http://bdigital.unal.edu.co/68324/
- Palabra clave:
- 53 Física / Physics
5 Ciencias naturales y matemáticas / Science
VHDL
FPGA
Operación
Raíz Cuadrada
VLSI
VHDL
FPGA
Operation
Square root
VLSI
- Rights
- openAccess
- License
- Atribución-NoComercial 4.0 Internacional
| Summary: | The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the accuracy is very high and there are no conditions or restrictions for the operation to be fulfilled. It also consumes much less hardware surface than other algorithms for calculating the square root of a number. The number entered is of fixed-point representation, it is parameterizable, that is, two constants N and M can define the size of the number, where N defines the number of bits in the integer part of the number and M defines the number of bits of the fractional part. |
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