Static and dynamic task mapping onto network on chip multiprocessors

Due to its scalability and flexibility, Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor System-on-Chip (MPSoC) design. As the manufacturing process scales down to the deep submicron domain and the complexity of the system increases, fault-tolerant design st...

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Autores:
Bolaños-Martínez, Freddy
Aedo, Jose Edison
Rivera-Vélez, Fredy
Tipo de recurso:
Article of journal
Fecha de publicación:
2014
Institución:
Universidad Nacional de Colombia
Repositorio:
Universidad Nacional de Colombia
Idioma:
spa
OAI Identifier:
oai:repositorio.unal.edu.co:unal/44570
Acceso en línea:
https://repositorio.unal.edu.co/handle/unal/44570
http://bdigital.unal.edu.co/34669/
Palabra clave:
Task mapping
Multiprocessor System-on-Chip (MPSoC)
Networks on Chip (NoC)
Population-based Incremental Learning (PBIL).
Rights
openAccess
License
Atribución-NoComercial 4.0 Internacional
Description
Summary:Due to its scalability and flexibility, Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor System-on-Chip (MPSoC) design. As the manufacturing process scales down to the deep submicron domain and the complexity of the system increases, fault-tolerant design strategies are gaining increased relevance. This paper exhibits the use of a Population-Based Incremental Learning (PBIL) algorithm aimed at finding the best mapping solutions at design time, as well as to finding the optimal remapping solution, in presence of single-node failures on the NoC. The optimization objectives in both cases are the application completion time and the network's peak bandwidth. A deterministic XY routing algorithm was used in order to simulate the traffic conditions in the network which has a 2D mesh topology. Obtained results are promising. The proposed algorithm exhibits a better performance, when compared with other reported approaches, as the problem size increases.