Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje

Algebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together...

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Autores:
Galindo Rodríguez, María José
Tipo de recurso:
Trabajo de grado de pregrado
Fecha de publicación:
2020
Institución:
Universidad Antonio Nariño
Repositorio:
Repositorio UAN
Idioma:
spa
OAI Identifier:
oai:repositorio.uan.edu.co:123456789/2213
Acceso en línea:
http://repositorio.uan.edu.co/handle/123456789/2213
Palabra clave:
Algebra de multiples valores lógicos.
Algebra of multiple logical values.
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openAccess
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Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
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network_name_str Repositorio UAN
repository_id_str
dc.title.es_ES.fl_str_mv Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
title Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
spellingShingle Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
Algebra de multiples valores lógicos.
Algebra of multiple logical values.
title_short Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
title_full Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
title_fullStr Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
title_full_unstemmed Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
title_sort Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
dc.creator.fl_str_mv Galindo Rodríguez, María José
dc.contributor.advisor.spa.fl_str_mv Duarte Gonzáles, Mario Enrrique
dc.contributor.author.spa.fl_str_mv Galindo Rodríguez, María José
dc.subject.es_ES.fl_str_mv Algebra de multiples valores lógicos.
topic Algebra de multiples valores lógicos.
Algebra of multiple logical values.
dc.subject.keyword.es_ES.fl_str_mv Algebra of multiple logical values.
description Algebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together with their corresponding logical operators (gates); which have been designed and implemented in both current and voltage modes, using CMOS technology. The best configuration for logic gates is in voltage mode because there is less power dissipation, as reported in the literature. In this work, a design was proposed for the circuits of the quaternary gates implementing CMOS technology in voltage mode with a smaller required area than the gates reported in recent works, the correct operation of the circuits was verified using the CADENCE Virtuoso program, as well as, the electrical characteristics: slew rate and power, by means of simulation. Finally, to evaluate the correct operation of the circuits, a quaternary demultiplexer was designed, built and simulated with the same tool.
publishDate 2020
dc.date.issued.spa.fl_str_mv 2020-07-21
dc.date.accessioned.none.fl_str_mv 2021-03-02T14:20:56Z
dc.date.available.none.fl_str_mv 2021-03-02T14:20:56Z
dc.type.spa.fl_str_mv Trabajo de grado (Pregrado y/o Especialización)
dc.type.coar.spa.fl_str_mv http://purl.org/coar/resource_type/c_7a1f
dc.type.coarversion.none.fl_str_mv http://purl.org/coar/version/c_970fb48d4fbd8a85
format http://purl.org/coar/resource_type/c_7a1f
dc.identifier.uri.none.fl_str_mv http://repositorio.uan.edu.co/handle/123456789/2213
dc.identifier.bibliographicCitation.spa.fl_str_mv PhD W. Merlijn van Spengen. High voltage amplifiers: how fast are they really?, March2016.
Wikipedia. Puerta not — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 16-julio-2020].
ME Romero Romero, E Mazina Martins, DCA Arigoni, A de M Nogueira, and ME Duarte-González. Voltage cmos quaternary gates for digital designs. In 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), pages 13–16. IEEE, 2019.
Shweta S Dawley and Pradnya A Gajbhiye. Design and comparative analysis of binary and quaternary logic circuits. In 2016 World Conference on Futuristic Trends in Research and Innovation for Social Welfare (Startup Conclave), pages 1–6. IEEE, 2016.
Claude Elwood Shannon. A mathematical theory of communication. Bell system technical journal, 27(3):379–423, 1948.
Milton ER Romero, Evandro M Martins, and Ricardo R Santos. Multiple valued logic algebra for the synthesis of digital circuits. In 2009 39th International Symposium on Multiple-Valued Logic, pages 262–267. IEEE, 2009.
Milton Ernesto Romero, Evandro Mazina Martins, Ricardo Ribeiro dos Santos, and Mario Enrique Duarte González. Universal set of cmos gates for the synthesis of multiple valued logic digital circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(3):736–749, 2013.
Ricardo Cunha G da Silva, Henri Boudinov, and Luigi Carro. A novel voltage-mode cmos quaternary logic design. IEEE Transactions on Electron devices, 53(6):1480–1483, 2006.
N. K. Naware, D. S. Khurge, and S. U. Bhandari. Review of quaternary algebra its logic circuits. In 2015 International Conference on Computing Communication Control and Automation, pages 969–973, 2015.
D. P. Borkute, P. Patel, and P. K. Dakhole. Delay performance and implementation of quaternary logic circuits. In 2015 International Conference on Computing Communication Control and Automation, pages 1008–1012, 2015.
A. Sheikholeslami, R. Yoshimura, and P. G. Gulak. Look-up tables (luts) for multiplevalued, combinational logic. In Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138), pages 264–269, 1998.
T. Hanyu, A. Mochizuki, and M. Kameyama. Multiple-valued dynamic source-coupled logic. In 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings., pages 207–212, 2003.
Z. Zilic and Z. G. Vranesic. Multiple-valued logic in fpgas. In Proceedings of 36th Midwest Symposium on Circuits and Systems, pages 1553–1556 vol.2, 1993.
M. H. A. Khan. Quaternary quantum algorithm for determining properties of quaternary logic function. In 14th International Conference on Computer and Information Technology (ICCIT 2011), pages 1–5, 2011.
M. H. A. Khan. Synthesis of incompletely specified multi-output quaternary function using quaternary quantum gates. In 2007 10th international conference on computer and information technology, pages 1–6, 2007.
K. M. Ishtiak, Safayat-Al-Imam, and N. A. Mahmud. Design and embodiment of larger quaternary multiplexer and demultiplexer. In 2014 International Conference on Electrical Engineering and Information Communication Technology, pages 1–5, 2014.
S. Hajare and P. Dakhole. Design of adders with quaternary logic. In 2015 International Conference on Industrial Instrumentation and Control (ICIC), pages 599–601, 2015.
M. S. E. Sendi, A. Khorami, S. Kananian, M. Sharifkhani, and A. M. Sodagar. Lowpower cmos voltage-mode quaternary latched comparator. In 2015 23rd Iranian Conference on Electrical Engineering, pages 1083–1088, 2015.
M. S. E. Sendi, M. Sharifkhani, and A. M. Sodagar. Cmos-compatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441, 2011.
Wu Haixia, Zhong Shunan, Sun Zhentao, Qu Xiaonan, and Chen Yueyang. Design of low-power quaternary flip-flop based on dynamic source-coupled logic. In 2011 International Conference on Electronics, Communications and Control (ICECC), pages 826–828. IEEE, 2011.
Evandro Mazina Martins and Milton Ernesto Romero Romero. Voltage mode multiple valued analog to quaternary mapping. IEEE Latin America Transactions, 16(3):792– 798, 2018.
Mohammad S Eslampanah Sendi, Mohammad Sharifkhani, and Amir M Sodagar. Cmoscompatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441. IEEE, 2011.
Enrique Mandado Pérez, Enrique Mandado, and Yago Mandado. Sistemas electrónicos digitales. Marcombo, 2007.
Wikipedia. Electrónica digital — wikipedia, la enciclopedia libre, 2019. [Internet; descargado 27-junio-2020].
Wikipedia. Circuito digital — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 12-julio-2020].
Wikipedia. Código binario — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020].
Wikipedia. Algebra de boole — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020].
MARIO ENRIQUE DUARTE GONZALEZ. Projeto e implementaC ,Ao dos operadores lógicos para a Álgebra de múltiplos valores. Master’s thesis, UNIVERSIDADE ´ FEDERAL DE MATO GROSSO DO SUL, 2011.
G. Prasad and R. Kusuma. Statistical (m-c) and static noise margin analysis of the sram cells. In 2013 Students Conference on Engineering and Systems (SCES), page 1, 2013.
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dc.identifier.reponame.spa.fl_str_mv reponame:Repositorio Institucional UAN
dc.identifier.repourl.spa.fl_str_mv repourl:https://repositorio.uan.edu.co/
url http://repositorio.uan.edu.co/handle/123456789/2213
identifier_str_mv PhD W. Merlijn van Spengen. High voltage amplifiers: how fast are they really?, March2016.
Wikipedia. Puerta not — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 16-julio-2020].
ME Romero Romero, E Mazina Martins, DCA Arigoni, A de M Nogueira, and ME Duarte-González. Voltage cmos quaternary gates for digital designs. In 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), pages 13–16. IEEE, 2019.
Shweta S Dawley and Pradnya A Gajbhiye. Design and comparative analysis of binary and quaternary logic circuits. In 2016 World Conference on Futuristic Trends in Research and Innovation for Social Welfare (Startup Conclave), pages 1–6. IEEE, 2016.
Claude Elwood Shannon. A mathematical theory of communication. Bell system technical journal, 27(3):379–423, 1948.
Milton ER Romero, Evandro M Martins, and Ricardo R Santos. Multiple valued logic algebra for the synthesis of digital circuits. In 2009 39th International Symposium on Multiple-Valued Logic, pages 262–267. IEEE, 2009.
Milton Ernesto Romero, Evandro Mazina Martins, Ricardo Ribeiro dos Santos, and Mario Enrique Duarte González. Universal set of cmos gates for the synthesis of multiple valued logic digital circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(3):736–749, 2013.
Ricardo Cunha G da Silva, Henri Boudinov, and Luigi Carro. A novel voltage-mode cmos quaternary logic design. IEEE Transactions on Electron devices, 53(6):1480–1483, 2006.
N. K. Naware, D. S. Khurge, and S. U. Bhandari. Review of quaternary algebra its logic circuits. In 2015 International Conference on Computing Communication Control and Automation, pages 969–973, 2015.
D. P. Borkute, P. Patel, and P. K. Dakhole. Delay performance and implementation of quaternary logic circuits. In 2015 International Conference on Computing Communication Control and Automation, pages 1008–1012, 2015.
A. Sheikholeslami, R. Yoshimura, and P. G. Gulak. Look-up tables (luts) for multiplevalued, combinational logic. In Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138), pages 264–269, 1998.
T. Hanyu, A. Mochizuki, and M. Kameyama. Multiple-valued dynamic source-coupled logic. In 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings., pages 207–212, 2003.
Z. Zilic and Z. G. Vranesic. Multiple-valued logic in fpgas. In Proceedings of 36th Midwest Symposium on Circuits and Systems, pages 1553–1556 vol.2, 1993.
M. H. A. Khan. Quaternary quantum algorithm for determining properties of quaternary logic function. In 14th International Conference on Computer and Information Technology (ICCIT 2011), pages 1–5, 2011.
M. H. A. Khan. Synthesis of incompletely specified multi-output quaternary function using quaternary quantum gates. In 2007 10th international conference on computer and information technology, pages 1–6, 2007.
K. M. Ishtiak, Safayat-Al-Imam, and N. A. Mahmud. Design and embodiment of larger quaternary multiplexer and demultiplexer. In 2014 International Conference on Electrical Engineering and Information Communication Technology, pages 1–5, 2014.
S. Hajare and P. Dakhole. Design of adders with quaternary logic. In 2015 International Conference on Industrial Instrumentation and Control (ICIC), pages 599–601, 2015.
M. S. E. Sendi, A. Khorami, S. Kananian, M. Sharifkhani, and A. M. Sodagar. Lowpower cmos voltage-mode quaternary latched comparator. In 2015 23rd Iranian Conference on Electrical Engineering, pages 1083–1088, 2015.
M. S. E. Sendi, M. Sharifkhani, and A. M. Sodagar. Cmos-compatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441, 2011.
Wu Haixia, Zhong Shunan, Sun Zhentao, Qu Xiaonan, and Chen Yueyang. Design of low-power quaternary flip-flop based on dynamic source-coupled logic. In 2011 International Conference on Electronics, Communications and Control (ICECC), pages 826–828. IEEE, 2011.
Evandro Mazina Martins and Milton Ernesto Romero Romero. Voltage mode multiple valued analog to quaternary mapping. IEEE Latin America Transactions, 16(3):792– 798, 2018.
Mohammad S Eslampanah Sendi, Mohammad Sharifkhani, and Amir M Sodagar. Cmoscompatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441. IEEE, 2011.
Enrique Mandado Pérez, Enrique Mandado, and Yago Mandado. Sistemas electrónicos digitales. Marcombo, 2007.
Wikipedia. Electrónica digital — wikipedia, la enciclopedia libre, 2019. [Internet; descargado 27-junio-2020].
Wikipedia. Circuito digital — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 12-julio-2020].
Wikipedia. Código binario — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020].
Wikipedia. Algebra de boole — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020].
MARIO ENRIQUE DUARTE GONZALEZ. Projeto e implementaC ,Ao dos operadores lógicos para a Álgebra de múltiplos valores. Master’s thesis, UNIVERSIDADE ´ FEDERAL DE MATO GROSSO DO SUL, 2011.
G. Prasad and R. Kusuma. Statistical (m-c) and static noise margin analysis of the sram cells. In 2013 Students Conference on Engineering and Systems (SCES), page 1, 2013.
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spelling Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)Acceso abiertohttps://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/openAccesshttp://purl.org/coar/access_right/c_abf2Duarte Gonzáles, Mario EnrriqueGalindo Rodríguez, María José2021-03-02T14:20:56Z2021-03-02T14:20:56Z2020-07-21http://repositorio.uan.edu.co/handle/123456789/2213PhD W. Merlijn van Spengen. High voltage amplifiers: how fast are they really?, March2016.Wikipedia. Puerta not — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 16-julio-2020].ME Romero Romero, E Mazina Martins, DCA Arigoni, A de M Nogueira, and ME Duarte-González. Voltage cmos quaternary gates for digital designs. In 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), pages 13–16. IEEE, 2019.Shweta S Dawley and Pradnya A Gajbhiye. Design and comparative analysis of binary and quaternary logic circuits. In 2016 World Conference on Futuristic Trends in Research and Innovation for Social Welfare (Startup Conclave), pages 1–6. IEEE, 2016.Claude Elwood Shannon. A mathematical theory of communication. Bell system technical journal, 27(3):379–423, 1948.Milton ER Romero, Evandro M Martins, and Ricardo R Santos. Multiple valued logic algebra for the synthesis of digital circuits. In 2009 39th International Symposium on Multiple-Valued Logic, pages 262–267. IEEE, 2009.Milton Ernesto Romero, Evandro Mazina Martins, Ricardo Ribeiro dos Santos, and Mario Enrique Duarte González. Universal set of cmos gates for the synthesis of multiple valued logic digital circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(3):736–749, 2013.Ricardo Cunha G da Silva, Henri Boudinov, and Luigi Carro. A novel voltage-mode cmos quaternary logic design. IEEE Transactions on Electron devices, 53(6):1480–1483, 2006.N. K. Naware, D. S. Khurge, and S. U. Bhandari. Review of quaternary algebra its logic circuits. In 2015 International Conference on Computing Communication Control and Automation, pages 969–973, 2015.D. P. Borkute, P. Patel, and P. K. Dakhole. Delay performance and implementation of quaternary logic circuits. In 2015 International Conference on Computing Communication Control and Automation, pages 1008–1012, 2015.A. Sheikholeslami, R. Yoshimura, and P. G. Gulak. Look-up tables (luts) for multiplevalued, combinational logic. In Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138), pages 264–269, 1998.T. Hanyu, A. Mochizuki, and M. Kameyama. Multiple-valued dynamic source-coupled logic. In 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings., pages 207–212, 2003.Z. Zilic and Z. G. Vranesic. Multiple-valued logic in fpgas. In Proceedings of 36th Midwest Symposium on Circuits and Systems, pages 1553–1556 vol.2, 1993.M. H. A. Khan. Quaternary quantum algorithm for determining properties of quaternary logic function. In 14th International Conference on Computer and Information Technology (ICCIT 2011), pages 1–5, 2011.M. H. A. Khan. Synthesis of incompletely specified multi-output quaternary function using quaternary quantum gates. In 2007 10th international conference on computer and information technology, pages 1–6, 2007.K. M. Ishtiak, Safayat-Al-Imam, and N. A. Mahmud. Design and embodiment of larger quaternary multiplexer and demultiplexer. In 2014 International Conference on Electrical Engineering and Information Communication Technology, pages 1–5, 2014.S. Hajare and P. Dakhole. Design of adders with quaternary logic. In 2015 International Conference on Industrial Instrumentation and Control (ICIC), pages 599–601, 2015.M. S. E. Sendi, A. Khorami, S. Kananian, M. Sharifkhani, and A. M. Sodagar. Lowpower cmos voltage-mode quaternary latched comparator. In 2015 23rd Iranian Conference on Electrical Engineering, pages 1083–1088, 2015.M. S. E. Sendi, M. Sharifkhani, and A. M. Sodagar. Cmos-compatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441, 2011.Wu Haixia, Zhong Shunan, Sun Zhentao, Qu Xiaonan, and Chen Yueyang. Design of low-power quaternary flip-flop based on dynamic source-coupled logic. In 2011 International Conference on Electronics, Communications and Control (ICECC), pages 826–828. IEEE, 2011.Evandro Mazina Martins and Milton Ernesto Romero Romero. Voltage mode multiple valued analog to quaternary mapping. IEEE Latin America Transactions, 16(3):792– 798, 2018.Mohammad S Eslampanah Sendi, Mohammad Sharifkhani, and Amir M Sodagar. Cmoscompatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441. IEEE, 2011.Enrique Mandado Pérez, Enrique Mandado, and Yago Mandado. Sistemas electrónicos digitales. Marcombo, 2007.Wikipedia. Electrónica digital — wikipedia, la enciclopedia libre, 2019. [Internet; descargado 27-junio-2020].Wikipedia. Circuito digital — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 12-julio-2020].Wikipedia. Código binario — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020].Wikipedia. Algebra de boole — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020].MARIO ENRIQUE DUARTE GONZALEZ. Projeto e implementaC ,Ao dos operadores lógicos para a Álgebra de múltiplos valores. Master’s thesis, UNIVERSIDADE ´ FEDERAL DE MATO GROSSO DO SUL, 2011.G. Prasad and R. Kusuma. Statistical (m-c) and static noise margin analysis of the sram cells. In 2013 Students Conference on Engineering and Systems (SCES), page 1, 2013.instname:Universidad Antonio Nariñoreponame:Repositorio Institucional UANrepourl:https://repositorio.uan.edu.co/Algebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together with their corresponding logical operators (gates); which have been designed and implemented in both current and voltage modes, using CMOS technology. The best configuration for logic gates is in voltage mode because there is less power dissipation, as reported in the literature. In this work, a design was proposed for the circuits of the quaternary gates implementing CMOS technology in voltage mode with a smaller required area than the gates reported in recent works, the correct operation of the circuits was verified using the CADENCE Virtuoso program, as well as, the electrical characteristics: slew rate and power, by means of simulation. Finally, to evaluate the correct operation of the circuits, a quaternary demultiplexer was designed, built and simulated with the same tool.El álgebra de múltiples valores lógicos surgió como una solución a los problemas presentes en los circuitos binarios (2 niveles lógicos): mal uso de área y potencia en circuitos integrados digitales. Entre las posibles alternativas se han presentado varias propuestas de álgebras cuaternarias (4 niveles lógicos), junto con sus correspondientes operadores (compuertas) lógicos; los cuales han sido diseñadas e implementadas tanto en modo corriente como en modo voltaje, utilizando tecnología CMOS. La mejor configuración para la compuertas lógicas es en modo voltaje debido que hay una menor disipación de potencia, tal como se ha reportado en la literatura. En este trabajo, se propuso un diseño para los circuitos de las compuertas cuaternarias implementando tecnología CMOS en modo voltaje con área requerida menor que las compuertas reportadas en trabajos recientes, se verificó el correcto funcionamiento de los circuito utilizando el programa CADENCE Virtuoso, así como, las características eléctricas: slew rate y potencia, por medio de simulación. Por último, para evaluar el funcionamiento correcto de los circuitos se diseñó, construyó y simuló con la misma herramienta un demultiplexor cuaternario.OtroIngeniero(a) Electrónico(a)PregradoCosto total del proyecto $3’503.182. Financiación propia $1’635.000. Financiación UAN $980.000PresencialspaUniversidad Antonio NariñoIngeniería ElectrónicaFacultad de Ingeniería Mecánica, Electrónica y BiomédicaBogotá - SurAlgebra de multiples valores lógicos.Algebra of multiple logical values.Diseño de compuertas lógicas cuaternarias CMOS en modo voltajeTrabajo de grado (Pregrado y/o Especialización)http://purl.org/coar/resource_type/c_7a1fhttp://purl.org/coar/version/c_970fb48d4fbd8a85ORIGINAL2020AutorizacióndeAutores.jpg2020AutorizacióndeAutores.jpgAutorización de autores.image/jpeg905954https://repositorio.uan.edu.co/bitstreams/39feef8a-67d3-4577-a2ca-3ee356cc1ee2/download02e7e2725e103d927356ecd73c438bf2MD522020MariaJoseGalindoRodriguez.pdf2020MariaJoseGalindoRodriguez.pdfTrabajo de grado.application/pdf1082964https://repositorio.uan.edu.co/bitstreams/d0aff6de-939e-4c60-a6cc-6a55738cc4b2/download882e4d8782b717c027f56a6cbc60d561MD54CC-LICENSElicense_rdflicense_rdfapplication/rdf+xml; charset=utf-8811https://repositorio.uan.edu.co/bitstreams/51c83fe7-717d-4c40-b2bb-c1c127fd8de6/download9868ccc48a14c8d591352b6eaf7f6239MD55LICENSElicense.txtlicense.txttext/plain; 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