Implementación del algoritmo Threefish-256 en hardware reconfigurable
This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-...
- Autores:
-
Nieto-Ramírez, Nathaly
Nieto-Londoño, Rubén Darío
- Tipo de recurso:
- Fecha de publicación:
- 2014
- Institución:
- Universidad Santo Tomás
- Repositorio:
- Repositorio Institucional USTA
- Idioma:
- spa
- OAI Identifier:
- oai:repository.usta.edu.co:11634/36117
- Acceso en línea:
- http://revistas.ustabuca.edu.co/index.php/ITECKNE/article/view/725
http://hdl.handle.net/11634/36117
- Palabra clave:
- Rights
- License
- Copyright (c) 2018 ITECKNE
| Summary: | This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-5 present in the development system XUPV5-LX110T. Place and route results show that the design Threefish-256 iterative round has a throughput of 551Mbps. |
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