Digital analog converter for the extraction of test signals from mixed integrated circuits
The construction of integrated circuits involves testing the correct operation of its internal blocks. For this, a common practice is the integration of functional blocks to stimulate the internal subsystems and extract the responses to those stimuli. In this article, the design and simulation of a...
- Autores:
-
Simancas-García, José L.
MELÉNDEZ, FARID
R. González, Ramón E.
Cárdenas, César
- Tipo de recurso:
- Article of journal
- Fecha de publicación:
- 2021
- Institución:
- Corporación Universidad de la Costa
- Repositorio:
- REDICUC - Repositorio CUC
- Idioma:
- eng
- OAI Identifier:
- oai:repositorio.cuc.edu.co:11323/8844
- Acceso en línea:
- https://hdl.handle.net/11323/8844
https://repositorio.cuc.edu.co/
- Palabra clave:
- Digital analog converter
Signals
Mixed integrated circuits
- Rights
- embargoedAccess
- License
- CC0 1.0 Universal
| id |
RCUC2_9203a6a8988f987021148a8893c3beba |
|---|---|
| oai_identifier_str |
oai:repositorio.cuc.edu.co:11323/8844 |
| network_acronym_str |
RCUC2 |
| network_name_str |
REDICUC - Repositorio CUC |
| repository_id_str |
|
| dc.title.spa.fl_str_mv |
Digital analog converter for the extraction of test signals from mixed integrated circuits |
| title |
Digital analog converter for the extraction of test signals from mixed integrated circuits |
| spellingShingle |
Digital analog converter for the extraction of test signals from mixed integrated circuits Digital analog converter Signals Mixed integrated circuits |
| title_short |
Digital analog converter for the extraction of test signals from mixed integrated circuits |
| title_full |
Digital analog converter for the extraction of test signals from mixed integrated circuits |
| title_fullStr |
Digital analog converter for the extraction of test signals from mixed integrated circuits |
| title_full_unstemmed |
Digital analog converter for the extraction of test signals from mixed integrated circuits |
| title_sort |
Digital analog converter for the extraction of test signals from mixed integrated circuits |
| dc.creator.fl_str_mv |
Simancas-García, José L. MELÉNDEZ, FARID R. González, Ramón E. Cárdenas, César |
| dc.contributor.author.spa.fl_str_mv |
Simancas-García, José L. MELÉNDEZ, FARID R. González, Ramón E. Cárdenas, César |
| dc.subject.spa.fl_str_mv |
Digital analog converter Signals Mixed integrated circuits |
| topic |
Digital analog converter Signals Mixed integrated circuits |
| description |
The construction of integrated circuits involves testing the correct operation of its internal blocks. For this, a common practice is the integration of functional blocks to stimulate the internal subsystems and extract the responses to those stimuli. In this article, the design and simulation of a circuit for the extraction of the response signals of the devices under test in analog and mixed-signal integrated circuits is presented. The extraction block is a 2-stage 5-bit segmented A/D converter, operating at a sampling frequency of 10 MHz, implemented in a 0.12 µm technological process, which can be powered with 1.5 Vdc. This proposal offers a reduction in the area consumed, by requiring fewer comparators than other similar solutions found in the literature. |
| publishDate |
2021 |
| dc.date.accessioned.none.fl_str_mv |
2021-11-08T13:11:53Z |
| dc.date.available.none.fl_str_mv |
2021-11-08T13:11:53Z |
| dc.date.issued.none.fl_str_mv |
2021 |
| dc.date.embargoEnd.none.fl_str_mv |
2022-09-17 |
| dc.type.spa.fl_str_mv |
Artículo de revista |
| dc.type.coar.fl_str_mv |
http://purl.org/coar/resource_type/c_2df8fbb1 |
| dc.type.coar.spa.fl_str_mv |
http://purl.org/coar/resource_type/c_6501 |
| dc.type.content.spa.fl_str_mv |
Text |
| dc.type.driver.spa.fl_str_mv |
info:eu-repo/semantics/article |
| dc.type.redcol.spa.fl_str_mv |
http://purl.org/redcol/resource_type/ART |
| dc.type.version.spa.fl_str_mv |
info:eu-repo/semantics/acceptedVersion |
| format |
http://purl.org/coar/resource_type/c_6501 |
| status_str |
acceptedVersion |
| dc.identifier.issn.spa.fl_str_mv |
03029743 |
| dc.identifier.uri.spa.fl_str_mv |
https://hdl.handle.net/11323/8844 |
| dc.identifier.doi.spa.fl_str_mv |
10.1007/978-3-030-86653-2_15 |
| dc.identifier.instname.spa.fl_str_mv |
Corporación Universidad de la Costa |
| dc.identifier.reponame.spa.fl_str_mv |
REDICUC - Repositorio CUC |
| dc.identifier.repourl.spa.fl_str_mv |
https://repositorio.cuc.edu.co/ |
| identifier_str_mv |
03029743 10.1007/978-3-030-86653-2_15 Corporación Universidad de la Costa REDICUC - Repositorio CUC |
| url |
https://hdl.handle.net/11323/8844 https://repositorio.cuc.edu.co/ |
| dc.language.iso.none.fl_str_mv |
eng |
| language |
eng |
| dc.relation.references.spa.fl_str_mv |
Simancas-García, J.L.: Diagnóstico de Circuitos Integrados Analógicos y de Comunicaciones. INGE@UAN - Tendencias en la Ingeniería 1(2), 7–19 (2011) Kundert, K., et al.: Design of mixed-signal systems-on-a-chip. IEEE Trans. Comput.-Aided Des. Integr. Circuita Syst. 19(12), 1561–1571 (2000) Zorian, Y., Marinissen, E., Dey, S.:Testing embedded-core-based sys- tem chips. In: IEEE Computer, pp. 52–60. Junio (1999) Hafed, M., Abaskharoun, N., Roberts, G.: A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits. IEEE J. Solid-State Circuits 37(4), 499–514 (2002) Hafed, M., Roberts, G.: A stand-alone integrated excitation/extraction systems for analog BIST application. In: IEEE 2000 Costum Integrated Circuit Conference, p. 4. IEEE (2000) Hafed, M., Roberts, G.: Techniques for high-frequency integrated test and measurement. IEEE Trans. Instrument. Measur. 52(16), 1780–1786 (2003) Zorian, Y.: System-chips test strategies. In: 35th Design Automation Conference 1998, San Francisco, p. 6. ACM (1998) Albustani, H.: Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis. Prüfung, 182 p. Dissertation (Ph.D.). Universität Duisburg-Essen. Fakultät für Ingenieurwissenschaften (2004) Dillinger, T.: VLSI Engineering, p. 863. Prentice-Hall, Estados Unidos (1988) Deschamps, J.-P.: Diseño de circuitos integrados de aplicación especifica ASIC, p. 385. Paraninfo, España (1994) Pucknell, D., Eshraghian, K.: Basic VLSI design, 3rd edn., p. 495. Prentice-Hall, Australia (1993) Dufort, B., Roberts, G.: Signal generation using periodic single and multi- bit sigma-delta modulated streams, p. 10 (1997) Dufort, B., Roberts, G.: Optimized periodic sigma-delta bitstreams for analog signal generation, vol. 4, p. 4 Haurie, X., Roberts, G.: Arbitrary-precision signal generation for mixed-signal built-in-self-test. IEEE Trans. Circuits Syst.—II Analog Digital Signal Process. 45(11), 1425–1432 (1998) Hawrysh, E., Roberts, G.: An integration of memory-based analog signal generation into current dft architectures. IEEE Trans. Instrument. Measur. 47(3), 748–759 (1998) Simancas-García, J.L., Caicedo-Ortiz, J.G.: Modelo computacional de un modulador ∑-∆ de 2° orden para la generación de señales de prueba en circuitos integrados analógicos. INGE@UAN - Tendencias en la Ingeniería 5(9), 43–55 (2014) Rubio, A., et al.: Diseño de circuitos y sistemas integrados, p. 446. Alfaomega, Mexico (2005) Soria Olivas, E., et al.: Tratamiento digital de señales: Problemas y ejercicios resueltos, p. 400. Prentice-Hall, España (2003) Aziz, P., Sorensen, H., Van Der Spiegel, J.: An overview of sigma-delta converters: how a 1-bit ADC achieves more than 16-bit resolution. IEEE Sig. Process. Magazine, 61–84 (1996) Proakis, J., Manolakis, D.: Tratamiento digital de señales: Principios, algoritmos, y aplicaciones, 3rd edn. Prentice-Hall, España (2003) Franco, S.: Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edn., p. 680. MacGraw-Hill, Estados Unidos (2002) Rashid, M.: Circuitos Microelectrónicos: Análisis y Diseño, p. 990. International Thomson, México (1999) Sedra, A., Smith, K.: Circuitos Microelectrónicos, 4th edn., p. 1232. Oxford University, México (1998) Van De Plassche, R., Baltus, M.: An 8-bit 100-MHZ full-Nyquist analog-to-digital converter. IEEE J. Solid-State Circuits 23(6), 1334–1344 (1988) Simancas-García, J.L.: Diseño de un Amplificador Operacional CMOS de Amplio Ancho de Banda y Alta Ganancia para Aplicaciones de Alta Velocidad. In: IngeCUC, vol. 9, no. 1 (2013) Sicard, E.: Microwind & Dsch User’s Manual Version 2, p. 110. National Institute of Applied Sciences, Toulouse, Francia (2002) Pavlidis, A., Louërat, M.-M., Faehn, E., Kumar, A., Stratigopoulos, H.-G.: SymBIST: symmetry-based analog and mixed-signal built-in self-test for functional safety. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6), 2580–2593 (2021) Thaker, N.B., Ashok, R., Manikandan, S., Nambath, N., Gupta, S.: A cost-effective solution for testing high-performance integrated circuits. IEEE Trans. Compon. Packag. Manuf. Technol. 11(4), 557–564 (2021) Stratigopoulos, H.-G., Streitwieser, C.: Adaptive test with test escape estimation for mixed-signal ICs. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 37(10), 2125–2138 (2017) Shi, J., Deng, Y., Wang, Z., He, Q.: A combined method for analog circuit fault diagnosis based on dependence matrices and intelligent classifiers. IEEE Trans. Instrument. Measur. 69(3), 782–793 (2019) Canelas, A., Póvoa, R., Martins, R., Lourenço, N., Guilherme, J., Carvalho, J.P.: FUZYE: a fuzzy c-means analog IC yield optimization using evolutionary-based algorithms. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 39(1), 1–13 (2018) Sehgal, A., Liu, F., Ozev, S., Chakrabarty, K.: Test planning for mixed-signal SOCS with wrapped analog cores. In: Design Automation and Test in Europe Conference and Exhibition, Munich, 2005, pp. 50–55. IEEE Computer Society, Munich (2005) |
| dc.rights.spa.fl_str_mv |
CC0 1.0 Universal |
| dc.rights.uri.spa.fl_str_mv |
http://creativecommons.org/publicdomain/zero/1.0/ |
| dc.rights.accessrights.spa.fl_str_mv |
info:eu-repo/semantics/embargoedAccess |
| dc.rights.coar.spa.fl_str_mv |
http://purl.org/coar/access_right/c_f1cf |
| rights_invalid_str_mv |
CC0 1.0 Universal http://creativecommons.org/publicdomain/zero/1.0/ http://purl.org/coar/access_right/c_f1cf |
| eu_rights_str_mv |
embargoedAccess |
| dc.format.mimetype.spa.fl_str_mv |
application/pdf |
| dc.publisher.spa.fl_str_mv |
Springer International Publishing |
| dc.source.spa.fl_str_mv |
Lecture Notes in Computer Science |
| institution |
Corporación Universidad de la Costa |
| dc.source.url.spa.fl_str_mv |
https://www.springerprofessional.de/en/digital-analog-converter-for-the-extraction-of-test-signals-from/19648702 |
| bitstream.url.fl_str_mv |
https://repositorio.cuc.edu.co/bitstreams/3fb74d88-e258-4f49-96c8-137110d6a31b/download https://repositorio.cuc.edu.co/bitstreams/76f25a14-69a6-43b4-8ecd-6fe4916a8ff1/download https://repositorio.cuc.edu.co/bitstreams/018d7706-7477-4d45-90bd-edfcbca5251a/download https://repositorio.cuc.edu.co/bitstreams/996334c6-da9a-45e3-93ab-c153bbbcf696/download https://repositorio.cuc.edu.co/bitstreams/a75308de-34d2-4724-807f-7769018eb340/download |
| bitstream.checksum.fl_str_mv |
3f74779431599be5b0a99423b2fb5991 42fd4ad1e89814f5e4a476b409eb708c e30e9215131d99561d40d6b0abbe9bad c1025b9aaca03b1b4093dbaa0cda2416 46f10512dcf3dc51475673877a9bbb3f |
| bitstream.checksumAlgorithm.fl_str_mv |
MD5 MD5 MD5 MD5 MD5 |
| repository.name.fl_str_mv |
Repositorio de la Universidad de la Costa CUC |
| repository.mail.fl_str_mv |
repdigital@cuc.edu.co |
| _version_ |
1828166838535585792 |
| spelling |
Simancas-García, José L.MELÉNDEZ, FARIDR. González, Ramón E.Cárdenas, César2021-11-08T13:11:53Z2021-11-08T13:11:53Z20212022-09-1703029743https://hdl.handle.net/11323/884410.1007/978-3-030-86653-2_15Corporación Universidad de la CostaREDICUC - Repositorio CUChttps://repositorio.cuc.edu.co/The construction of integrated circuits involves testing the correct operation of its internal blocks. For this, a common practice is the integration of functional blocks to stimulate the internal subsystems and extract the responses to those stimuli. In this article, the design and simulation of a circuit for the extraction of the response signals of the devices under test in analog and mixed-signal integrated circuits is presented. The extraction block is a 2-stage 5-bit segmented A/D converter, operating at a sampling frequency of 10 MHz, implemented in a 0.12 µm technological process, which can be powered with 1.5 Vdc. This proposal offers a reduction in the area consumed, by requiring fewer comparators than other similar solutions found in the literature.Simancas-García, José L.MELÉNDEZ, FARID-will be generated-orcid-0000-0001-7007-0109-600R. González, Ramón E.Cárdenas, César-will be generated-orcid-0000-0001-6662-6899-600application/pdfengSpringer International PublishingCC0 1.0 Universalhttp://creativecommons.org/publicdomain/zero/1.0/info:eu-repo/semantics/embargoedAccesshttp://purl.org/coar/access_right/c_f1cfLecture Notes in Computer Sciencehttps://www.springerprofessional.de/en/digital-analog-converter-for-the-extraction-of-test-signals-from/19648702Digital analog converterSignalsMixed integrated circuitsDigital analog converter for the extraction of test signals from mixed integrated circuitsArtículo de revistahttp://purl.org/coar/resource_type/c_6501http://purl.org/coar/resource_type/c_2df8fbb1Textinfo:eu-repo/semantics/articlehttp://purl.org/redcol/resource_type/ARTinfo:eu-repo/semantics/acceptedVersionSimancas-García, J.L.: Diagnóstico de Circuitos Integrados Analógicos y de Comunicaciones. INGE@UAN - Tendencias en la Ingeniería 1(2), 7–19 (2011)Kundert, K., et al.: Design of mixed-signal systems-on-a-chip. IEEE Trans. Comput.-Aided Des. Integr. Circuita Syst. 19(12), 1561–1571 (2000)Zorian, Y., Marinissen, E., Dey, S.:Testing embedded-core-based sys- tem chips. In: IEEE Computer, pp. 52–60. Junio (1999)Hafed, M., Abaskharoun, N., Roberts, G.: A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits. IEEE J. Solid-State Circuits 37(4), 499–514 (2002)Hafed, M., Roberts, G.: A stand-alone integrated excitation/extraction systems for analog BIST application. In: IEEE 2000 Costum Integrated Circuit Conference, p. 4. IEEE (2000)Hafed, M., Roberts, G.: Techniques for high-frequency integrated test and measurement. IEEE Trans. Instrument. Measur. 52(16), 1780–1786 (2003)Zorian, Y.: System-chips test strategies. In: 35th Design Automation Conference 1998, San Francisco, p. 6. ACM (1998)Albustani, H.: Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis. Prüfung, 182 p. Dissertation (Ph.D.). Universität Duisburg-Essen. Fakultät für Ingenieurwissenschaften (2004)Dillinger, T.: VLSI Engineering, p. 863. Prentice-Hall, Estados Unidos (1988)Deschamps, J.-P.: Diseño de circuitos integrados de aplicación especifica ASIC, p. 385. Paraninfo, España (1994)Pucknell, D., Eshraghian, K.: Basic VLSI design, 3rd edn., p. 495. Prentice-Hall, Australia (1993)Dufort, B., Roberts, G.: Signal generation using periodic single and multi- bit sigma-delta modulated streams, p. 10 (1997)Dufort, B., Roberts, G.: Optimized periodic sigma-delta bitstreams for analog signal generation, vol. 4, p. 4Haurie, X., Roberts, G.: Arbitrary-precision signal generation for mixed-signal built-in-self-test. IEEE Trans. Circuits Syst.—II Analog Digital Signal Process. 45(11), 1425–1432 (1998)Hawrysh, E., Roberts, G.: An integration of memory-based analog signal generation into current dft architectures. IEEE Trans. Instrument. Measur. 47(3), 748–759 (1998)Simancas-García, J.L., Caicedo-Ortiz, J.G.: Modelo computacional de un modulador ∑-∆ de 2° orden para la generación de señales de prueba en circuitos integrados analógicos. INGE@UAN - Tendencias en la Ingeniería 5(9), 43–55 (2014)Rubio, A., et al.: Diseño de circuitos y sistemas integrados, p. 446. Alfaomega, Mexico (2005)Soria Olivas, E., et al.: Tratamiento digital de señales: Problemas y ejercicios resueltos, p. 400. Prentice-Hall, España (2003)Aziz, P., Sorensen, H., Van Der Spiegel, J.: An overview of sigma-delta converters: how a 1-bit ADC achieves more than 16-bit resolution. IEEE Sig. Process. Magazine, 61–84 (1996)Proakis, J., Manolakis, D.: Tratamiento digital de señales: Principios, algoritmos, y aplicaciones, 3rd edn. Prentice-Hall, España (2003)Franco, S.: Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edn., p. 680. MacGraw-Hill, Estados Unidos (2002)Rashid, M.: Circuitos Microelectrónicos: Análisis y Diseño, p. 990. International Thomson, México (1999)Sedra, A., Smith, K.: Circuitos Microelectrónicos, 4th edn., p. 1232. Oxford University, México (1998)Van De Plassche, R., Baltus, M.: An 8-bit 100-MHZ full-Nyquist analog-to-digital converter. IEEE J. Solid-State Circuits 23(6), 1334–1344 (1988)Simancas-García, J.L.: Diseño de un Amplificador Operacional CMOS de Amplio Ancho de Banda y Alta Ganancia para Aplicaciones de Alta Velocidad. In: IngeCUC, vol. 9, no. 1 (2013)Sicard, E.: Microwind & Dsch User’s Manual Version 2, p. 110. National Institute of Applied Sciences, Toulouse, Francia (2002)Pavlidis, A., Louërat, M.-M., Faehn, E., Kumar, A., Stratigopoulos, H.-G.: SymBIST: symmetry-based analog and mixed-signal built-in self-test for functional safety. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6), 2580–2593 (2021)Thaker, N.B., Ashok, R., Manikandan, S., Nambath, N., Gupta, S.: A cost-effective solution for testing high-performance integrated circuits. IEEE Trans. Compon. Packag. Manuf. Technol. 11(4), 557–564 (2021)Stratigopoulos, H.-G., Streitwieser, C.: Adaptive test with test escape estimation for mixed-signal ICs. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 37(10), 2125–2138 (2017)Shi, J., Deng, Y., Wang, Z., He, Q.: A combined method for analog circuit fault diagnosis based on dependence matrices and intelligent classifiers. IEEE Trans. Instrument. Measur. 69(3), 782–793 (2019)Canelas, A., Póvoa, R., Martins, R., Lourenço, N., Guilherme, J., Carvalho, J.P.: FUZYE: a fuzzy c-means analog IC yield optimization using evolutionary-based algorithms. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 39(1), 1–13 (2018)Sehgal, A., Liu, F., Ozev, S., Chakrabarty, K.: Test planning for mixed-signal SOCS with wrapped analog cores. In: Design Automation and Test in Europe Conference and Exhibition, Munich, 2005, pp. 50–55. IEEE Computer Society, Munich (2005)PublicationORIGINALDigital Analog Converter for the Extraction of Test Signals from Mixed Integrated Circuits.pdfDigital Analog Converter for the Extraction of Test Signals from Mixed Integrated Circuits.pdfapplication/pdf28608https://repositorio.cuc.edu.co/bitstreams/3fb74d88-e258-4f49-96c8-137110d6a31b/download3f74779431599be5b0a99423b2fb5991MD51CC-LICENSElicense_rdflicense_rdfapplication/rdf+xml; charset=utf-8701https://repositorio.cuc.edu.co/bitstreams/76f25a14-69a6-43b4-8ecd-6fe4916a8ff1/download42fd4ad1e89814f5e4a476b409eb708cMD52LICENSElicense.txtlicense.txttext/plain; charset=utf-83196https://repositorio.cuc.edu.co/bitstreams/018d7706-7477-4d45-90bd-edfcbca5251a/downloade30e9215131d99561d40d6b0abbe9badMD53THUMBNAILDigital Analog Converter for the Extraction of Test Signals from Mixed Integrated Circuits.pdf.jpgDigital Analog Converter for the Extraction of Test Signals from Mixed Integrated Circuits.pdf.jpgimage/jpeg39804https://repositorio.cuc.edu.co/bitstreams/996334c6-da9a-45e3-93ab-c153bbbcf696/downloadc1025b9aaca03b1b4093dbaa0cda2416MD54TEXTDigital Analog Converter for the Extraction of Test Signals from Mixed Integrated Circuits.pdf.txtDigital Analog Converter for the Extraction of Test Signals from Mixed Integrated Circuits.pdf.txttext/plain1065https://repositorio.cuc.edu.co/bitstreams/a75308de-34d2-4724-807f-7769018eb340/download46f10512dcf3dc51475673877a9bbb3fMD5511323/8844oai:repositorio.cuc.edu.co:11323/88442024-09-17 14:16:28.16http://creativecommons.org/publicdomain/zero/1.0/CC0 1.0 Universalopen.accesshttps://repositorio.cuc.edu.coRepositorio de la Universidad de la Costa CUCrepdigital@cuc.edu.coQXV0b3Jpem8gKGF1dG9yaXphbW9zKSBhIGxhIEJpYmxpb3RlY2EgZGUgbGEgSW5zdGl0dWNpw7NuIHBhcmEgcXVlIGluY2x1eWEgdW5hIGNvcGlhLCBpbmRleGUgeSBkaXZ1bGd1ZSBlbiBlbCBSZXBvc2l0b3JpbyBJbnN0aXR1Y2lvbmFsLCBsYSBvYnJhIG1lbmNpb25hZGEgY29uIGVsIGZpbiBkZSBmYWNpbGl0YXIgbG9zIHByb2Nlc29zIGRlIHZpc2liaWxpZGFkIGUgaW1wYWN0byBkZSBsYSBtaXNtYSwgY29uZm9ybWUgYSBsb3MgZGVyZWNob3MgcGF0cmltb25pYWxlcyBxdWUgbWUobm9zKSBjb3JyZXNwb25kZShuKSB5IHF1ZSBpbmNsdXllbjogbGEgcmVwcm9kdWNjacOzbiwgY29tdW5pY2FjacOzbiBww7pibGljYSwgZGlzdHJpYnVjacOzbiBhbCBww7pibGljbywgdHJhbnNmb3JtYWNpw7NuLCBkZSBjb25mb3JtaWRhZCBjb24gbGEgbm9ybWF0aXZpZGFkIHZpZ2VudGUgc29icmUgZGVyZWNob3MgZGUgYXV0b3IgeSBkZXJlY2hvcyBjb25leG9zIHJlZmVyaWRvcyBlbiBhcnQuIDIsIDEyLCAzMCAobW9kaWZpY2FkbyBwb3IgZWwgYXJ0IDUgZGUgbGEgbGV5IDE1MjAvMjAxMiksIHkgNzIgZGUgbGEgbGV5IDIzIGRlIGRlIDE5ODIsIExleSA0NCBkZSAxOTkzLCBhcnQuIDQgeSAxMSBEZWNpc2nDs24gQW5kaW5hIDM1MSBkZSAxOTkzIGFydC4gMTEsIERlY3JldG8gNDYwIGRlIDE5OTUsIENpcmN1bGFyIE5vIDA2LzIwMDIgZGUgbGEgRGlyZWNjacOzbiBOYWNpb25hbCBkZSBEZXJlY2hvcyBkZSBhdXRvciwgYXJ0LiAxNSBMZXkgMTUyMCBkZSAyMDEyLCBsYSBMZXkgMTkxNSBkZSAyMDE4IHkgZGVtw6FzIG5vcm1hcyBzb2JyZSBsYSBtYXRlcmlhLg0KDQpBbCByZXNwZWN0byBjb21vIEF1dG9yKGVzKSBtYW5pZmVzdGFtb3MgY29ub2NlciBxdWU6DQoNCi0gTGEgYXV0b3JpemFjacOzbiBlcyBkZSBjYXLDoWN0ZXIgbm8gZXhjbHVzaXZhIHkgbGltaXRhZGEsIGVzdG8gaW1wbGljYSBxdWUgbGEgbGljZW5jaWEgdGllbmUgdW5hIHZpZ2VuY2lhLCBxdWUgbm8gZXMgcGVycGV0dWEgeSBxdWUgZWwgYXV0b3IgcHVlZGUgcHVibGljYXIgbyBkaWZ1bmRpciBzdSBvYnJhIGVuIGN1YWxxdWllciBvdHJvIG1lZGlvLCBhc8OtIGNvbW8gbGxldmFyIGEgY2FibyBjdWFscXVpZXIgdGlwbyBkZSBhY2Npw7NuIHNvYnJlIGVsIGRvY3VtZW50by4NCg0KLSBMYSBhdXRvcml6YWNpw7NuIHRlbmRyw6EgdW5hIHZpZ2VuY2lhIGRlIGNpbmNvIGHDsW9zIGEgcGFydGlyIGRlbCBtb21lbnRvIGRlIGxhIGluY2x1c2nDs24gZGUgbGEgb2JyYSBlbiBlbCByZXBvc2l0b3JpbywgcHJvcnJvZ2FibGUgaW5kZWZpbmlkYW1lbnRlIHBvciBlbCB0aWVtcG8gZGUgZHVyYWNpw7NuIGRlIGxvcyBkZXJlY2hvcyBwYXRyaW1vbmlhbGVzIGRlbCBhdXRvciB5IHBvZHLDoSBkYXJzZSBwb3IgdGVybWluYWRhIHVuYSB2ZXogZWwgYXV0b3IgbG8gbWFuaWZpZXN0ZSBwb3IgZXNjcml0byBhIGxhIGluc3RpdHVjacOzbiwgY29uIGxhIHNhbHZlZGFkIGRlIHF1ZSBsYSBvYnJhIGVzIGRpZnVuZGlkYSBnbG9iYWxtZW50ZSB5IGNvc2VjaGFkYSBwb3IgZGlmZXJlbnRlcyBidXNjYWRvcmVzIHkvbyByZXBvc2l0b3Jpb3MgZW4gSW50ZXJuZXQgbG8gcXVlIG5vIGdhcmFudGl6YSBxdWUgbGEgb2JyYSBwdWVkYSBzZXIgcmV0aXJhZGEgZGUgbWFuZXJhIGlubWVkaWF0YSBkZSBvdHJvcyBzaXN0ZW1hcyBkZSBpbmZvcm1hY2nDs24gZW4gbG9zIHF1ZSBzZSBoYXlhIGluZGV4YWRvLCBkaWZlcmVudGVzIGFsIHJlcG9zaXRvcmlvIGluc3RpdHVjaW9uYWwgZGUgbGEgSW5zdGl0dWNpw7NuLCBkZSBtYW5lcmEgcXVlIGVsIGF1dG9yKHJlcykgdGVuZHLDoW4gcXVlIHNvbGljaXRhciBsYSByZXRpcmFkYSBkZSBzdSBvYnJhIGRpcmVjdGFtZW50ZSBhIG90cm9zIHNpc3RlbWFzIGRlIGluZm9ybWFjacOzbiBkaXN0aW50b3MgYWwgZGUgbGEgSW5zdGl0dWNpw7NuIHNpIGRlc2VhIHF1ZSBzdSBvYnJhIHNlYSByZXRpcmFkYSBkZSBpbm1lZGlhdG8uDQoNCi0gTGEgYXV0b3JpemFjacOzbiBkZSBwdWJsaWNhY2nDs24gY29tcHJlbmRlIGVsIGZvcm1hdG8gb3JpZ2luYWwgZGUgbGEgb2JyYSB5IHRvZG9zIGxvcyBkZW3DoXMgcXVlIHNlIHJlcXVpZXJhIHBhcmEgc3UgcHVibGljYWNpw7NuIGVuIGVsIHJlcG9zaXRvcmlvLiBJZ3VhbG1lbnRlLCBsYSBhdXRvcml6YWNpw7NuIHBlcm1pdGUgYSBsYSBpbnN0aXR1Y2nDs24gZWwgY2FtYmlvIGRlIHNvcG9ydGUgZGUgbGEgb2JyYSBjb24gZmluZXMgZGUgcHJlc2VydmFjacOzbiAoaW1wcmVzbywgZWxlY3Ryw7NuaWNvLCBkaWdpdGFsLCBJbnRlcm5ldCwgaW50cmFuZXQsIG8gY3VhbHF1aWVyIG90cm8gZm9ybWF0byBjb25vY2lkbyBvIHBvciBjb25vY2VyKS4NCg0KLSBMYSBhdXRvcml6YWNpw7NuIGVzIGdyYXR1aXRhIHkgc2UgcmVudW5jaWEgYSByZWNpYmlyIGN1YWxxdWllciByZW11bmVyYWNpw7NuIHBvciBsb3MgdXNvcyBkZSBsYSBvYnJhLCBkZSBhY3VlcmRvIGNvbiBsYSBsaWNlbmNpYSBlc3RhYmxlY2lkYSBlbiBlc3RhIGF1dG9yaXphY2nDs24uDQoNCi0gQWwgZmlybWFyIGVzdGEgYXV0b3JpemFjacOzbiwgc2UgbWFuaWZpZXN0YSBxdWUgbGEgb2JyYSBlcyBvcmlnaW5hbCB5IG5vIGV4aXN0ZSBlbiBlbGxhIG5pbmd1bmEgdmlvbGFjacOzbiBhIGxvcyBkZXJlY2hvcyBkZSBhdXRvciBkZSB0ZXJjZXJvcy4gRW4gY2FzbyBkZSBxdWUgZWwgdHJhYmFqbyBoYXlhIHNpZG8gZmluYW5jaWFkbyBwb3IgdGVyY2Vyb3MgZWwgbyBsb3MgYXV0b3JlcyBhc3VtZW4gbGEgcmVzcG9uc2FiaWxpZGFkIGRlbCBjdW1wbGltaWVudG8gZGUgbG9zIGFjdWVyZG9zIGVzdGFibGVjaWRvcyBzb2JyZSBsb3MgZGVyZWNob3MgcGF0cmltb25pYWxlcyBkZSBsYSBvYnJhIGNvbiBkaWNobyB0ZXJjZXJvLg0KDQotIEZyZW50ZSBhIGN1YWxxdWllciByZWNsYW1hY2nDs24gcG9yIHRlcmNlcm9zLCBlbCBvIGxvcyBhdXRvcmVzIHNlcsOhbiByZXNwb25zYWJsZXMsIGVuIG5pbmfDum4gY2FzbyBsYSByZXNwb25zYWJpbGlkYWQgc2Vyw6EgYXN1bWlkYSBwb3IgbGEgaW5zdGl0dWNpw7NuLg0KDQotIENvbiBsYSBhdXRvcml6YWNpw7NuLCBsYSBpbnN0aXR1Y2nDs24gcHVlZGUgZGlmdW5kaXIgbGEgb2JyYSBlbiDDrW5kaWNlcywgYnVzY2Fkb3JlcyB5IG90cm9zIHNpc3RlbWFzIGRlIGluZm9ybWFjacOzbiBxdWUgZmF2b3JlemNhbiBzdSB2aXNpYmlsaWRhZA== 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