VHDL Optimized Model of a Multiplier in Finite Fields

In this research, an analysis of the behavior of the multiplier in finite fields GF is performed, considering the generalized architecture of LFSR component (records displacements linear feedback), this for the purpose of generating a VHDL description optimized, applying concepts of structural analysis, description parameterized components, mathematisation, this in order to obtain the generalized representation model. Thus achieving the concurrent sequential circuit description nature. tabulating the terms was performed according to the time variable and position in the circuit, components of a sequence generator based on a linear feedback function, so that the circuit was patterned in generic expression operator "concatenation" available in VHDL for hardware configuration, model consumption of hardware resources are estimated at the level of logical operators, so that the proposed method shows their contributions in terms of optimizing the efficient modeling of advanced logic systems, which can be extrapolated to more complex components. Leading to the conclusion that the model developed simplifies the description of parallel circuits, high efficiency from a mathematical modeling approach to hardware description.

• Tipo de recurso: article
• Fecha de publicación: 2017
• Institución: Pontificia Universidad Javeriana
• Repositorio: Repositorio Universidad Javeriana
• Idioma: eng
• OAI Identifier: oai:repository.javeriana.edu.co:10554/25630
• Acceso en línea: http://revistas.javeriana.edu.co/index.php/iyu/article/view/195; http://hdl.handle.net/10554/25630
• Rights: openAccess
• License: Copyright (c) 2017 Cecilia Esperanza Sandoval-Ruiz