A self-adaptive hardware architecture with fault tolerance capabilities

This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other adaptive capabilities of the system are self-routing, self-placement and runtime selfconfiguration. Additionally, it is described as an example application and a software tool that has been implemented to facilitate the development of applications to test the system.

• Autores: Moreno, Juan Manuel; Soto Vargas, Javier Evandro; Cabestany, Joan
• Tipo de recurso: Article of investigation
• Fecha de publicación: 2013
• Institución: Escuela Colombiana de Ingeniería Julio Garavito
• Repositorio: Repositorio Institucional ECI
• Idioma: eng
• OAI Identifier: oai:repositorio.escuelaing.edu.co:001/2311
• Acceso en línea: https://repositorio.escuelaing.edu.co/handle/001/2311; https://doi.org/10.1016/j.neucom.2012.10.038; https://www.sciencedirect.com/science/article/abs/pii/S0925231213004293
• Palabra clave: Computación tolerante a fallos; Autoestabilización (Computadores); Autoenrutamiento (Administración de redes de computadores); Fault-tolerant computing; Self-stabilization (Computer science); Self-routing (Computer network management); Self-adaptive; Self-placement; Self-routing; Self-replication; MIMD; Dynamic fault tolerance
• Rights: closedAccess
• License: http://purl.org/coar/access_right/c_14cb